From ecc350ca5c2eb50be8309c5f14f8bf0d87db9a02 Mon Sep 17 00:00:00 2001 From: Moon Flower Date: Mon, 12 Oct 2026 08:46:23 +0330 Subject: a --- src/baremetal/link_aarch64.ld | 37 +++++++++++++++++++++++++++++++++++++ 1 file changed, 37 insertions(+) create mode 100644 src/baremetal/link_aarch64.ld (limited to 'src/baremetal/link_aarch64.ld') diff --git a/src/baremetal/link_aarch64.ld b/src/baremetal/link_aarch64.ld new file mode 100644 index 0000000..6740f21 --- /dev/null +++ b/src/baremetal/link_aarch64.ld @@ -0,0 +1,37 @@ +OUTPUT_ARCH(aarch64) +OUTPUT_FORMAT(elf64-littleaarch64) +ENTRY(_start) + +/* virt RAM starts at 0x40000000. The PL011 UART is at 0x09000000, outside this. */ +MEMORY +{ + RAM (rwx) : ORIGIN = 0x40000000, LENGTH = 48M +} + +SECTIONS +{ + .text : { + KEEP(*(.text.init)) + *(.text .text.*) + } > RAM + .rodata : { + *(.rodata .rodata.*) + } > RAM + .data : { + *(.data .data.*) + } > RAM + .bss : { + . = ALIGN(16); + _sbss = .; + *(.bss .bss.*) + *(COMMON) + . = ALIGN(16); + _ebss = .; + } > RAM + .stack : { + . = ALIGN(16); + . += 64K; + _stack_top = .; + } > RAM + /DISCARD/ : { *(.eh_frame*) *(.comment) *(.note*) } +} -- cgit v1.2.3