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-rw-r--r--src/baremetal/start_riscv.S20
1 files changed, 20 insertions, 0 deletions
diff --git a/src/baremetal/start_riscv.S b/src/baremetal/start_riscv.S
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+/* RISC-V virt, machine mode, no firmware. Stack, clear bss, enter C. */
+.section .text.init
+.global _start
+_start:
+ /* FS = Dirty, so a compiler that emits float ops does not trap. */
+ li t0, 0x6000
+ csrs mstatus, t0
+ la sp, _stack_top
+ la t0, _sbss
+ la t1, _ebss
+1:
+ bgeu t0, t1, 2f
+ sd zero, 0(t0)
+ addi t0, t0, 8
+ j 1b
+2:
+ call bare_main
+3:
+ wfi
+ j 3b