src/baremetal/link_aarch64.ld


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OUTPUT_ARCH(aarch64)
OUTPUT_FORMAT(elf64-littleaarch64)
ENTRY(_start)

/* virt RAM starts at 0x40000000. The PL011 UART is at 0x09000000, outside this. */
MEMORY
{
	RAM (rwx) : ORIGIN = 0x40000000, LENGTH = 48M
}

SECTIONS
{
	.text : {
		KEEP(*(.text.init))
		*(.text .text.*)
	} > RAM
	.rodata : {
		*(.rodata .rodata.*)
	} > RAM
	.data : {
		*(.data .data.*)
	} > RAM
	.bss : {
		. = ALIGN(16);
		_sbss = .;
		*(.bss .bss.*)
		*(COMMON)
		. = ALIGN(16);
		_ebss = .;
	} > RAM
	.stack : {
		. = ALIGN(16);
		. += 64K;
		_stack_top = .;
	} > RAM
	/DISCARD/ : { *(.eh_frame*) *(.comment) *(.note*) }
}